1. Field
Embodiments relate to a method of under-filling semiconductor die in a die stack and a semiconductor device formed thereby.
2. Description of the Related Art
The strong growth in demand for portable consumer electronics is driving the need for high-capacity storage devices. Non-volatile semiconductor memory devices, such as flash memory storage cards, are becoming widely used to meet the ever-growing demands on digital information storage and exchange. Their portability, versatility and rugged design, along with their high reliability and large capacity, have made such memory devices ideal for use in a wide variety of electronic devices, including for example digital cameras, digital music players, video game consoles, PDAs and cellular telephones.
While a wide variety of packaging configurations are known, flash memory storage cards may in general be fabricated as system-in-a-package (SiP) or multichip modules (MCM), where a plurality of die are mounted on a substrate in a so-called three-dimensional stacked configuration. The substrate may in general include a rigid, dielectric base having a conductive layer etched on one or both sides. Electrical connections are formed between the die and the conductive layer(s), and the conductive layer(s) in the substrate provide an electric lead structure for connection of the die to a host device. Once electrical connections between the die and substrate are made, the assembly is then typically encased in a molding compound to provide a protective package.
Many semiconductor packages use wire bonding to electrically connect the semiconductor die with the substrate. In wire bonded packages, wires are connected between bond pads on the surface of each semiconductor die at one end, and portions of the substrate at the other end. In order to provide a bonding position for the bond wires to attach to the bond pads on each semiconductor die, the bond wires require vertical spacing between the semiconductor die, or horizontal offset stacking of the semiconductor die. Similarly, in order to provide space for the wire bonds on the substrate, portions of the substrate extend out beyond the edges of the die mounted thereon, thereby requiring a larger substrate.
In view of the trend toward smaller package sizes and increased storage densities, alternative technologies are being developed for electrically connecting the semiconductor die in a package without wire bonds and/or without a substrate. One such alternative technology uses through silicon vias (TSV). TSV technology involves forming holes, or vias, in the semiconductor die, typically at the wafer level. These holes are plated and filled with an electrical conductor, such as copper. Signals to and from the die in the stack are carried through the vias, so that the space otherwise needed for wire bonding may be omitted. Omission of the bond wires also improves signal to noise ratio and yield rates, as bond wires are fragile and can break or short together during the package fabrication process. It is also possible to omit the substrate in packages formed by TSV technology, as the finished package can be soldered directly to a host device such as a printed circuit board.
An example of a conventional TSV semiconductor chip stack 20 is shown in the cross-sectional view of FIG. 1. The chip stack 20 includes a plurality of semiconductor die 22-28. Although four die are shown, it is known to provide more or less semiconductor die in alternative configurations. The integrated circuitry in each of the semiconductor die 22-28 is electrically connected to through silicon vias 30 and interconnect pads 32 formed in each die. The number and location of vias 30 and pads 32 may vary in different configurations. In some semiconductor devices, such as flash memory, the vias 30 and interconnect pads 32 in each die in the die stack may align with each other as shown in FIG. 1. Thus, electrical signals may be communicated to and from each of the die through the vias 30 and interconnect pads 32. Solder bumps 36 may be provided for affixing the semiconductor chip stack 20 to a substrate, such as a printed circuit board. The chip stack and substrate may then be encapsulated to form a finished semiconductor package.
The interconnect pads 32 are provided to allow the vias 30 in the respective die 22-26 to be electrically coupled to each other. It is known to form the interconnect pads 32 at the wafer level using copper-to-copper diffusion, solder bumping or some other metal bonding technique. Regardless, the height of interconnect pads results in a small space (e.g. 5-10 μm) between each of the die 22-28 in the die stack.
There are disadvantages to leaving the empty spaces between the die 22-28. First, the coefficient of thermal expansion of the silicon die and the metal interconnect pads are different. Thus, when the chip stack is heated during subsequent fabrication processes, these mismatched coefficients of thermal expansion can result in the separation of the interconnect pads 32 from the die 22-28 and die failure. Moreover, left unsealed, moisture ingress into the empty space can lead to corrosion of the interconnect pads 32.
It is therefore known to add a sealant 40 into the empty spaces between the die 22-28. The addition of sealant 40 encapsulates the interconnect pads 32 and serves to redistribute the stresses resulting from thermal mismatch at the interconnect pads 32 over a wider area. Moreover, the sealant 40 prevents moisture from corroding the interconnect pads.
However, conventional methods for under-filling the spaces between the respective die involve introducing a liquid sealant, and allowing that sealant to fill the entire empty space by capillary action. However, with the drive to reduce the size of semiconductor packages, the interconnect pads 32 are being made with lower and lower profiles. At current interconnect pad profiles, it may happen that surface tension and the viscosity of the liquid sealant prevent the sealant 40 from fully under-filling the space between the die, resulting in voids 42. Voids 42 tend to propagate, for example during heating and expansion of the gasses in voids 42. This propagation of any voids can result in exposure of the interconnect pads, and even delamination of one or more die from the chip stack.